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IP-XACT, also known as IEEE 1685,cite-ref-1[1] is an XML format that defines and describes individual, re-usable electronic circuit designs (individual pieces of intellectual property, or IPs) to facilitate their use in creating integrated circuits (i.e. microchips). IP-XACT was created by the SPIRIT Consortium as a standard to enable automated configuration and integration through toolscite-ref-2[2] and evolving into an IEEE standard.

The goals of the standard are

• to ensure delivery of compatible component descriptions, such as IPs, from multiple component vendors,

• to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments),

• to describe configurable components using metadata, and

• to enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators).

Approved as IEEE 1685-2009 on December 9, 2009, published on February 18, 2010.cite-ref-3[3] Superseded by IEEE 1685-2014. IEEE 1685-2009 was adopted as IEC 62014-4:2015. In June 2023, the supplemental material for standard IEEE 1685-2022 IP-XACT was approved by Accellera.cite-ref-4[4]

• Overview

• Supporting companies and software

• See also

• References

• Further reading

• External links

Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.

All documents will have the following basic titular attributes spirit:vendor, spirit:library, spirit:name, spirit:version.

A document typically represents one of:

• bus specification, giving its signals and protocol etc.;

• leaf IP block data sheet;

• or a hierarchic component wiring diagram that describes a sub-system by connecting up or abstracting other components made up of spirit:componentInstance and spirit:interconnection elements.

For each port of a component there will be a spirit:busInterface element in the document. This may have a spirit:signalMap that gives the mapping of the formal net names in the interface to the names used in a corresponding formal specification of the port. A simple wiring tool will use the signal map to know which net on one interface to connect to which net on another instance of the same formal port on another component.

There may be various versions of a component referenced in the document, each as a spirit:view element, relating to different versions of a design: typical levels are gate-level, RTL and TLM. Each view typically contains a list of filenames as a spirit:fileSet that implement the design at that level of abstraction in appropriate language, like Verilog, C++ or PSL.

Non-functional data present includes the programmer's view with a list of spirit:register declarations inside a spirit:memoryMap or spirit:addressBlock.

• Arteris cite-ref-5[5]- Magillem Connectivity,cite-ref-6[6] Magillem Registers,cite-ref-7[7] CSRCompilercite-ref-8[8] and FlexNoC5cite-ref-9[9]

• Cadence - JasperGold cite-ref-10[10] and Interconnect Workbench (IWB) cite-ref-11[11]

• Synopsys, Inc cite-ref-12[12]

• Agnisys cite-ref-13[13]

• Defacto Technologies cite-ref-14[14]

• EDAUtils cite-ref-15[15]

• Magillem (now part of Arteris) cite-ref-16[16]

• Semifore (now part of Arteris) cite-ref-17[17]

• Xilinx (now part of AMD)

• Lattice

• SystemRDL

cite-note-11. ↑ "IEEE Standards Association". IEEE Standards Association. Retrieved 2023-10-27.

cite-note-22. ↑ IP-XACT Working Group

cite-note-33. ↑ IEEE 1685-2009, ISBN 978-0-7381-6160-0

cite-note-44. ↑ "IP-XACT". www.accellera.org. Retrieved 2023-10-27.

cite-note-55. ↑ "Arteris". Retrieved 2023-10-27.

cite-note-66. ↑ "Magillem Connectivity – Arteris". Retrieved 2023-10-27.

cite-note-77. ↑ "Magillem Registers – Arteris". Retrieved 2023-10-27.

cite-note-88. ↑ "CSRCompiler – Arteris". Retrieved 2023-10-27.

cite-note-99. ↑ "FlexNoC 5 Interconnect IP – Arteris". Retrieved 2023-10-27.

cite-note-1010. ↑ Cadence's JasperGold Control and Status Register App

cite-note-1111. ↑ Cadence Interconnect Workbench

cite-note-1212. ↑ Synopsys, Inc

cite-note-1313. ↑ Agnisys IDesignSpec

cite-note-1414. ↑ Defacto SoC Compiler

cite-note-1515. ↑ EDAUtils

cite-note-1616. ↑ Magillem Design Services

cite-note-1717. ↑ Semifore, Inc

• 1685-2022 - IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2023. doi:10.1109/IEEESTD.2023.10054520. ISBN 978-1-5044-9448-9.

• 1685-2014 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2014. doi:10.1109/IEEESTD.2014.6898803. ISBN 978-0-7381-9226-0.

• 1685-2009 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows. 2010. doi:10.1109/IEEESTD.2010.5417309. ISBN 978-0-7381-6160-0.

• IEEE/IEC International Standard - IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. 2015. doi:10.1109/IEEESTD.2015.7066223. ISBN 978-2-8322-2265-2.

• SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform

• citerefberman2006Berman, V. (April 2006). "Standards: The P1685 IP-XACT IP Metadata Standard". IEEE Design & Test of Computers. 23 (4): 316–317. doi:10.1109/MDT.2006.104. S2CID 206459094.

• citerefkruijtzervaumorinvan-der-wolfde-kock2008Kruijtzer, W.; Vaumorin, E.; Van Der Wolf, P.; De Kock, E.; Stuyt, J.; Ecker, W.; Mayer, A.; Hustin, S.; Amerijckx, C.; De Paoli, S. (2008). Industrial IP integration flows based on IP-XACT™ standards. DATE'08. Proceedings of the conference on Design, automation and test in Europe. pp. 32–37. CiteSeerX 10.1.1.455.8801. doi:10.1145/1403375.1403386. ISBN 978-3-9810801-3-1.

• IEEE 1685-2022

• IP-XACT at Accellera

• XML Schema at Accellera

• BusDefs at Accellera